Electronic devices as well some optical devices, are typically manufactured by a sequence of steps, each of which can deposit and/or modify a layer formed in (or on) a substrate surface. In many cases such a surface is a wafer having opposing sides.
Forming layers on a wafer can be directional, non-directional or some combination thereof. In a directional formation process, a wafer may be situated on a chuck or platen. A layer may then be formed, by deposition or the like, on a top surface of a wafer. In a non-directional formation process, a wafer may be situated within a wafer boat, or other carrying structure, that can expose both sides of a wafer. A wafer boat may be situated within a furnace or the like, and a layer may be formed on both sides of a wafer.
Devices formed on substrates are typically manufactured in large numbers by taking advantage of uniformity across a substrate surface. As device features continue to shrink, it can be more difficult to achieve uniformity due to various effects. One effect that can result in variations in device features can be mechanical stress introduced by one or more layers. An example of such a feature variation will now be described.
Referring now to FIGS. 7A to 7F, a conventional method of forming shallow trench isolation (STI) in a semiconductor substrate is shown in a series of side cross sectional views.
FIG. 7A shows a substrate 700 having a first side 702 and a second side 704. A substrate 700 can include a wafer of essentially monocrystalline silicon, as but one example. A layer of silicon dioxide 706 may be formed on a first side 702. In addition, a layer of silicon nitride may be formed in a non-directional manner. Consequently, there may be a first side silicon nitride layer 708-0 formed over a first side 702, and a second side silicon nitride layer 708-1 formed over a second side 704.
FIG. 7B shows the formation of an etch mask 710 from a first side silicon nitride layer 708-0. An etch mask may be formed by first developing an etch mask pattern with photoresist according to photolithographic or other methods. A first side silicon nitride layer 708-0 may then be etched using the developed photoresist as a mask, to form an etch mask 710.
FIG. 7C shows a substrate 700 after substrate etching that may form substrate trenches, one of which is shown as item 712. FIG. 7B shows how a substrate 700 may be warped due to stress and/or mismatches in stress between a first side silicon nitride layer 708-0 (now an etch mask 710) and second side silicon nitride layer 708-1.
It is understood that the various features of FIGS. 7A to 7F are shown in exaggerated form. In particular wafers may be about eight inches in diameter, while trench widths can be as small as 0.2 μm or less. Likewise, the particular curvature shown is exaggerated to better understand the drawbacks of a conventional approach such as that shown in FIGS. 7A to 7F.
FIG. 7D shows the formation of a trench dielectric 714. A trench dielectric 714 may be formed with a directional process over a first substrate side 702. In one particular example, a trench dielectric 714 may include silicon dioxide formed with a high density plasma, as but one example.
FIG. 7E shows a planarization step that can planarize a trench filling layer 714. A planarization step may include chemical-mechanical polishing. As but one example, a substrate 700 may be placed, first side 702 down, on a moving polishing pad that can be covered with a slurry.
Ideally, chemical-mechanical polishing can result in trenches 712 that may be filled to a uniform height. However, as shown in FIG. 7F, due to mechanical stress that may warp a substrate, trenches 712-0 in a center portion of a substrate 700-0 may be filled to a lower height than trenches 712-{fraction (1/2)} in more peripheral portions 700-1 and 700-2. Differences in trench fill height may adversely affect isolation properties of a resulting integrated circuit device.
In light of the above, it would be desirable to arrive at some way of reducing feature variations that may be introduced by mechanical stress of one or more layers. Even more particularly, it would be desirable to arrive at some way of improving a dielectric polishing in a device formed on a substrate.